Semiconductor device and manufacturing method thereof

ABSTRACT

A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2012-185332 filed onAug. 24, 2012 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to semiconductor devices, and morespecifically, to a technique that can be suitably applied to asemiconductor device, for example, with an active element in a wiringlayer.

There have been known techniques for providing an active element in awiring layer of a semiconductor device. Such a semiconductor device canswitch its function by use of the active element without changing thelayout of semiconductor elements formed at a semiconductor substrate.Thus, the technique can manufacture a plurality of types ofsemiconductor devices with different functions using the semiconductorsubstrate with the same layout of the semiconductor elements over thesubstrate. In this case, the manufacturing costs of the semiconductordevices can be reduced.

For example, Japanese Unexamined Patent Publication No. 2010-141230discloses a semiconductor device and a manufacturing method thereof. Thesemiconductor device includes a semiconductor substrate, a first wiringlayer, a semiconductor layer, a gate insulating film, and a gateelectrode. The first wiring layer includes an insulating layer formedover the semiconductor substrate, and a first wiring embedded in thesurface of the insulating layer. The semiconductor layer is positionedover the first wiring layer. The gate insulating film is positionedabove or below the semiconductor layer. The gate electrode is positionedon the opposite side to the semiconductor layer via the gate insulatingfilm. At this time, the semiconductor layer, the gate insulating film,and the gate electrode form a transistor as the active element. Forexample, one first wiring can be used as the gate insulating film.Specifically, a cap insulating film for preventing the diffusion of thefirst wiring layer can be used as the gate insulating film. In thatcase, the gate insulating film is formed under the semiconductor layer.

In order to reduce power consumption (save power) of the active elementin the wiring layer as described above, it is effective to use a CMOSinverter. This is because the use of the CMOS inverter as a switch cansuppress the flow-through current through the inverter. The CMOSinverter includes a P-type MOS transistor and an N-type MOS transistorin the same wiring layer. In this case, both a P-type semiconductorlayer and an N-type semiconductor layer which are made of differentmaterials are required to be provided in the same wiring layer.

When using the technique disclosed in the above Japanese UnexaminedPaten Publication No. 2010-141230, specifically, the following structurecan be proposed. The active element, that is, the CMOS inverter in thewiring layer, includes the P-type MOS transistor and the N-type MOStransistor. In each of the MOS transistors, one first wiring in thefirst wiring layer serves as the gate electrode, the cap insulating filmfor preventing the diffusion over first wiring layer serves as the gateinsulating film, and a semicondutor layer is provided in a predeterminedshape over the cap insulating film. The P-type semiconductor layer andthe N-type semiconductor layer are disposed spaced apart from eachother. Both layers are embedded in an interlayer insulating layer.

In the related art, Non-Patent Document 1 (2012 Symposium on VLSITechnology Digest of Technical Papers, 123-124 (2012)) discloses aninverter circuit using an oxide semiconductor layer. Non-Patent Document2 (2011 Symposium on VLSI Technology Digest of Technical Papers, 120-121(2011)) discloses a LSI incorporating an oxide semiconductor layer in amultilayer wiring layer. Further, Non-Patent Document 3 (2011 IEEEInternational Electron Devices Meeting (IEDM), 155-158 (2011)) disclosesa transistor device structure using an oxide semiconductor layer.

PCT Patent Publication WO 2010/010802, Non-Patent Document 4 (Appl.Phys. Lett. 93, 032113(2008)), and Non-Patent Document 5 (Appl. Phys.Lett. 97, 072111(2010)) discloses a p-channel thin film transistor. Thep-channel thin film transistor (field-effect transistor) includes a thinfilm made of stannous oxide (SnO) deposited as a channel layer over asubstrate of the thin film transistor. A source/drain electrode isformed using a laminated film of Ni/Au or a Pt film.

RELATED ART DOCUMENTS Patent Documents

-   [Patent Document 1]-   Japanese Unexamined Patent Publication No. 2010-141230-   [Patent Document 2]-   WO2010/010802

Non-Patent Documents

-   [Non-Patent Document 1]-   K. Kaneko et. al., “Operation of Functional Circuit Elements using    BEOL-Transistor with InGaZnO Channel for On-chip High/Low Voltage    Bridging I/Os and High-Current Switches”, 2012 Symposium on VLSI    Technology Digest of Technical Papers, 123-124 (2012).-   [Non-Patent Document 2]-   K. Kaneko et. al., “A Novel BEOL-Transistor (BETr) with InGaZnO    Embedded in Cu-Interconnects for On-chip High Voltage I/Os in    Standard CMOS LSIs”, 2011 Symposium on VLSI Technology Digest of    Technical Papers, 120-121 (2011).-   [Non-Patent Document 3]-   K. Kaneko et. al., “High Reliable BEOL-Transistor with    Oxygen-controlled InGaZnO and Gate/Drain Offset Design for High/Low    Voltage Bridging I/O Operations”, 2011 IEE International Electron    Devices Meeting (IEDM), 155-158 (2011).-   [Non-Patent Document 4]-   Yoichi Ogo, et. al., “p-channel thin-film transistor using p-type    oxide semiconductor, SnO”, Appl. Phys. Lett. 93, 032113 (2008).-   [Non-Patent Document 5]-   Hisato Yabuta, et. al., “Sputtering formation of p-type SnO    thin-film transistors on glass toward oxide complimentary circuits”,    Appl. Phys. Lett. 97, 072111 (2010).

SUMMARY

In the above CMOS inverter using the technique disclosed in JapaneseUnexamined Patent Publication No. 2010-141230, individual manufacturingprocesses for the P-type semiconductor layer and the N-typesemiconductor layer are very important because the P-type and N-typesemiconductor layers are formed of different materials in the samewiring layer. The individual manufacturing processes involve firstforming one type (for example, P-type) of semiconductor layer, and thenforming the other type (for example, N-type) of semiconductor layer. Theindividual manufacturing processes will be specifically described below.

First, a P-type semiconductor film and a hard mask for a P-typesemiconductor layer are laminated over a cap insulating film in thatorder. Then, the P-type semiconductor film and the P hard mask areetched into a desired shape. In this way, a P-type semiconductor layerwith its surface covered with the P hard mask is formed. The P-typesemiconductor layer has its side exposed to the outside. Subsequently,an N-type semiconductor film and a hard mask for an N-type semiconductorlayer are laminated in that order over an element isolation isulatingfilm and the P hard mask. Then, the N-type semiconductor film and the Nhard mask are etched into a desired shape. In this way, an N-typesemiconductor layer with its surface covered with the N hard mask isformed.

In the above process, when depositing the N-type semiconductor film, theside of the P-type semiconductor layer under the P hard mask is partlyexposed. Thus, the N-type semiconductor film might be brought intocontact with the side of the P-type semiconductor layer. As a result,the material of the P-type semiconductor film might possibly be diffusedinto the N-type semiconductor layer, or the material of the N-typesemiconductor layer might possibly be diffused into the P-typesemiconductor film, which would degrade or modify the properties of theP-type semiconductor layer. The same goes for the structure of acombination of the N-type semiconductor layer and the P-typesemiconductor layer which are formed in the reversed order. Techniquesare required to form both the N-type semiconductor layer and the P-typesemiconductor layer in the same wiring layer without influences on theproperties of the semiconductor layer.

Other problems and new features of the present invention will be betterunderstood after a reading of the following detailed description of thepresent specification in connection with the accompanying drawings.

According to one embodiment of the present invention, an insulating filmis provided at one of the N-type semiconductor layer and the P-typesemicondutor layer to cover the sides of the semiconductor layer (andhard mask layer).

In the one embodiment of the present invention, the N-type semiconductorlayer and the P-type semiconductor layer can be provided together in thesame wiring layer without influences on the properties of thesemiconductor layer.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A is a cross-sectional view showing the structure of asemiconductor device according to a first embodiment of the presentinvention;

FIG. 1B is another cross-sectional view showing the structure of thesemiconductor device according to the first embodiment;

FIG. 2 is a plan view showing the structure of the semiconductor devicein the first embodiment;

FIG. 3A is a cross-sectional view showing a step of a manufacturingmethod of the semiconductor device in the first embodiment;

FIG. 3B is a cross-sectional view showing another step of themanufacturing method of the semiconductor device in the firstembodiment;

FIG. 3C is a cross-sectional view showing another step of themanufacturing method of the semiconductor device in the firstembodiment;

FIG. 3D is a cross-sectional view showing another step of themanufacturing method of the semiconductor device in the firstembodiment;

FIG. 3E is a cross-sectional view showing another step of themanufacturing method of the semiconductor device in the firstembodiment;

FIG. 3F is a cross-sectional view showing another step of themanufacturing method of the semiconductor device in the firstembodiment;

FIG. 3G is a cross-sectional view showing another step of themanufacturing method of the semiconductor device in the firstembodiment;

FIG. 3H is a cross-sectional view showing another step of themanufacturing method of the semiconductor device in the firstembodiment;

FIG. 3I is a cross-sectional view showing another step of themanufacturing method of the semiconductor device in the firstembodiment;

FIG. 3J is a cross-sectional view showing another step of the amanufacturing method of the semiconductor device in the firstembodiment;

FIG. 3K is a cross-sectional view showing another step of themanufacturing method of the semiconductor device in the firstembodiment;

FIG. 3L is a cross-sectional view showing another step of themanufacturing method of the semiconductor device in the firstembodiment;

FIG. 3M is a cross-sectional view showing another step of themanufacturing method of the semiconductor device in the firstembodiment;

FIG. 4A is a cross-sectional view showing a step of a manufacturingmethod of a semiconductor device without forming sidewalls;

FIG. 4B is a cross-sectional view showing another step of themanufacturing method of a semiconductor device without formingsidewalls;

FIG. 5A is a cross-sectional view showing a step of a manufacturingmethod of a semiconductor device with a coated insulating film for asidewall remaining;

FIG. 5B is a cross-sectional view showing another step of themanufacturing method of a semiconductor device with the coatedinsulating film for a sidewall remaining;

FIG. 5C is a cross-sectional view showing another step of themanufacturing method of a semiconductor device with the coatedinsulating film for a sidewall remaining;

FIG. 5D is a cross-sectional view showing another step of themanufacturing method of a semiconductor device with the coatedinsulating film for a sidewall remaining;

FIG. 6 is a table showing differences between the structure of thisembodiment and the structure shown in FIG. 5D;

FIG. 7 is a cross-sectional view showing a first modified example of thestructure of the semiconductor device according to the first embodiment;

FIG. 8 is a cross-sectional view showing a second modified example ofthe structure of the semiconductor device in the first embodiment;

FIG. 9A is a cross-sectional view showing a step of a manufacturingmethod of the semiconductor device in the second modified example of thefirst embodiment;

FIG. 9B is a cross-sectional view showing another step of themanufacturing method of the semiconductor device in the second modifiedexample of the first embodiment;

FIG. 10 is a cross-sectional view showing the structure of asemiconductor device according to a second embodiment of the invention;

FIG. 11 is a cross-sectional view showing the structure of asemiconductor device according to a third embodiment of the invention;

FIG. 12 is a cross-sectional view showing the structure of asemiconductor device according to a fourth embodiment of the invention;

FIG. 13A is a cross-sectional view showing a step of a manufacturingmethod of a semiconductor device according to the third embodiment;

FIG. 13B is a cross-sectional view showing another step of themanufacturing method of a semiconductor device in the third embodiment;

FIG. 13C is a cross-sectional view showing another step of themanufacturing method of a semiconductor device in the third embodiment;

FIG. 14 is a cross-sectional view showing the structure of asemiconductor device according to the fourth embodiment;

FIG. 15 is a graph showing contact characteristics between a materialfor a contact and an oxide semiconductor layer;

FIG. 16 is a cross-sectional view showing the structure of asemiconductor device according to a fifth embodiment of the invention;

FIG. 17 is a graph showing contact characteristics between the materialfor a contact and another oxide semiconductor layer;

FIG. 18 is a schematic cross-sectional view showing a composition of aninterface between a P-type oxide semicondutor layer and a source/drainelectrode of the semiconductor device in this embodiment;

FIG. 19 is a cross-sectional view showing an element for measuring theproperties of the semiconductor device in this embodiment; and

FIG. 20 is a graph showing the properties of the semiconductor device inthis embodiment.

DETAILED DESCRIPTION

Now, a semiconductor device and a manufacturing method thereof accordingto some preferred embodiments of the present invention will be describedbelow with reference to the accompanying drawings.

First Embodiment

The structure of a semiconductor device in a first embodiment of theinvention will be described below. FIGS. 1A, 1B, and 2 arecross-sectional views and a plan view showing the structure of thesemiconductor device in this embodiment. FIGS. 1A and 1B arecross-sectional views taken along the line A-A′ of FIG. 2. FIG. 1A showsa main part of FIG. 1B.

A semiconductor device 100 of this embodiment includes a first wiringlayer 150, a second wiring layer 170, a first transistor 200, and asecond transistor 300. The first wiring layer 150 includes a firstinterlayer insulating layer 152, and a first wiring 164 (210, 310)embedded in the surface of the first interlayer insulating layer 152.The second wiring layer 170 is formed over the first wiring layer 150.The second wiring layer 170 includes a cap insulating layer 171 coveringthe first wirings 164, 210, and 310 and the first interlayer insulatinglayer 152, a second interlayer insulating layer 172, and second wirings188, 289, and 389 embedded in the second interlayer insulating layer172. The first transistor 200 is provided in the first wiring layer 150and the second wiring layer 170, and is of a first conductive type (forexample, P-type). The second transistor 300 is provided in the firstwiring layer 150 and the second wiring layer 170, and is of a secondconductive type (for example, N-type) other than the first conductivetype.

The first transistor 200 includes a first gate electrode 210, the firstgate insulating film (171), a first oxide semiconductor layer 230, afirst hard mask 232, and first sidewalls 240. The first gate electrode210 is one of the first wirings. The first gate insulating film (171) isprovided over the first gate electrode 210, and includes a part of thecap insulating layer 171. The first oxide semiconductor layer 230 isprovided over the first gate insulating film (171). The first hard mask232 is provided over the first oxide semiconductor layer 230. Each firstsidewall 240 is provided aside from the second interlayer insulatinglayer 172 to cover the side of the first oxide semiconductor layer 230to exhibit insulating properties. The second transistor 300 includes thesecond gate electrode 310, a second gate insulating film (171), a secondoxide semiconductor layer 330, and a second hard mask 332. The secondgate electrode 310 is the other of the first wirings. The second gateinsulating film (171) is provided over the second gate electrode 310 tobe coupled to the first gate insulating film (171), including anotherpart of the cap insulating layer (171). The second oxide semiconductorlayer 330 is provided over the second insulating film (171). The secondhard mask 332 is provided over the second oxide semiconductor layer. Thefirst transistor 200 and the second transistor 300 are transistors ofopposite conductive types to form a complementary metal-oxidesemiconductor (CMOS).

With this arrangement, the first oxide semiconductor layer 230 under thefirst hard mask 232 previously has its sides covered with the firstsidewalls 240 when depositing the second oxide semiconductor layer 330.Thus, the first oxide semiconductor layer 230 is not in contact with theside of the second oxide semiconductor layer 330. As a result, there isno possibility that the first oxide semiconductor layer 230 modifies anddegrades its properties due to dispersion of the material of the firstoxide semiconductor layer 230 into the second oxide semiconductor layer330, or dispersion of the material of the second oxide semiconductorlayer 330 into the first oxide semiconductor layer 230. Thus, the N-typesemiconductor layer and the P-type semiconductor layer can coexisttogether in the same wiring layer without any influences on propertiesof each oxide semiconductor layer. The insulating film over the firstoxide semiconductor layer 230 is one layer of the first hard mask 232(having a thickness d01). Likewise, the insulating film over the secondoxide semiconductor layer 330 is also one layer of the second hard mask332 (having a thickness d02), which can easily make the thicknesses ofboth layers substantially the same. Contact holes for the source anddrain electrodes can be formed by etching in the same etching time.Thus, the contact characteristics of the respective oxide semiconductorlayers can be substantially the same.

Now, the semiconductor device 100 in the first embodiment of theinvention will be further described below.

The semiconductor device 100 further includes a semiconductor substrate101, a contact layer 130 provided over the semiconductor substrate 101,and a wiring layer 140 provided over the contact layer 130. Thesemiconductor substrate 101 is provided with semiconductor elements,such as a transistor or a capacity element. In an example shown,transistors 121 and 122 are formed. The transistors 121 and 122 areseparated by an element isolation layer 120. The contact layer 130includes an interlayer insulating layer 131 provided over thesemiconductor substrate 101, and contacts (source/drain electrode) 142embedded in the interlayer insulating layer. The wiring layer 140includes an interlayer insulating layer 132 provided over the interlayerinsulating layer 131, and wirings 144 embedded therein. The source/drainof each of the transistors 121 and 122 is coupled to the wiring 144 viathe contact (source/drain electrode) 142.

The first wiring layer 150 includes a cap insulating layer 151 providedover the wiring layer 140, and a first interlayer insulating layer 152provided over the cap insulating layer 151. The wiring layer 150 furtherincludes a via 162, and the first wiring 164 in addition to the abovefirst gate electrode 210 and the second gate electrode 310 provided overthe surface of a first interlayer insulating layer 152. The via 162 hasits lower end penetrating the cap insulating layer 151 to be coupled tothe wiring 144, and its upper end coupled to the first wiring 164. Thefirst wiring 164 is provided on the front side of the first interlayerinsulating layer 152. The first wiring 164, the first gate electrode210, and the second gate electrode 310 are provided in the same firstwiring layer 150.

The second wiring layer 170 includes the cap insulating layer 171provided over the first wiring layer 150, and the second interlayerinsulating layer 172 provided over the cap insulating layer 171. Thesecond wiring layer 170 further includes a via 189, and the secondwiring 188. The via 189 has its lower end penetrating the cap insulatinglayer 171 to be coupled to the first wiring 164, and its upper endcoupled to the second wiring 188. The second wiring 188 is provided onthe front side of the second interlayer insulating layer 172. The figureshows an example of the via 189 and the second wiring 188 of a dualdamascene structure.

The second wiring layer 170 further includes the first oxidesemiconductor layer 230 provided over the cap insulating layer 171, thefirst hard mask 232 provided over the first oxide semiconductor layer230, and the sidewalls 240 provided around the laminated structure ofthe first oxide semiconductor layer 230 and the first hard mask 232.Thus, the first gate electrode 210, the cap insulating layer 171 as thegate insulating film, and the first oxide semiconductor layer 230 formthe first transistor 200. The second wiring layer 170 further includesthe contact (source/drain electrode) 289, and the second wiring 288. Thecontact 289 has its lower end penetrating the first hard mask 232 to becoupled to the first oxide semiconductor layer 230, and its upper endcoupled to the second wiring 288. The second wiring 288 is provided onthe front side of the second interlayer insulating layer 172. The figureshows an example of the contact 289 and the second wiring 288 of thedual damascene structure.

Likewise, the second wiring layer 170 further includes the second oxidesemiconductor layer 330 provided over the cap insulating layer 171, andthe second hard mask 332 provided over the second oxide semiconductorlayer 330. Thus, the second gate electrode 310, the cap insulating layer171 as the gate insulating film, and the second oxide semiconductorlayer 330 form the second transistor 300. The second wiring layer 170further includes the contact (source/drain electrode) 389, and a secondwiring 388. The contact 389 has its lower end penetrating the secondhard mask 332 to be coupled to the second oxide semiconductor layer 330,and its upper end coupled to the second wiring 388. The second wiring388 is provided on the front side of the second interlayer insulatinglayer 172. The figure shows an example of the contact 389 and the secondwiring 138 of the dual damascene structure.

As mentioned above, the first transistor 200 and the second transistor300 form the CMOS in the wiring layer. The CMOS (each of transistors 200and 300) is formed across the first wiring layer 150 including the firstwirings as the gate electrodes 210 and 310, and the second wiring layer170 including channels (the oxide semiconductor layers 230 and 330) andsource/drain electrodes (the contacts 289 and 389).

In other words, the first transistor 200 of one conductive type includesthe first oxide semiconductor layer 230 as the channel, whereas thesecond transistor 300 of the other opposite conductive type includes thesecond oxide semiconductor layer 330 as the channel. Each of thetransistors includes the first wiring (Cu wiring) formed in the firstwiring layer 150 as the gate electrode 210 or 310, and a cap insulatinglayer 160 as the gate insulating film. The sidewalls 240 are formed overboth side walls of the first oxide semiconductor layer 230 as thechannel of the first transistor 200 and the first hard mask 232. Eachsidewall 240 serves as an element isolation film between the adjacenttransistors. The sidewall 240 has only to cover at least the side wallof the first oxide semiconductor layer 230 even if the sidewall 240 doesnot cover the side of the first hard mask 232.

The via 189 is formed in the second wiring layer 170 to establishelectrical coupling to the first wiring (Cu wiring) 14 thereunder. Atthe same time, the contact 289 electrically coupled to the first oxidesemiconductor layer 230 is formed via the first hard mask 232, whichserves as the source/drain electrode of the first transistor 200.Further, simultaneously, the contact 389 electrically coupled to thesecond oxide semiconductor layer 330 is formed via the second hard mask332, which serves as the source/drain electrode of the second transistor300. The combinations of the N-type and P-type transistors may include:the N-type first transistor 200 and the P-type second transistor 300;and the P-type first transistor 200 and the N-type second transistor300. The first transistor 200 and the second transistor 300 are coupledin series, and the first gate electrode 210 and the second gateelectrode 310 are electrically coupled together, which forms the CMOSinverter. In this embodiment, a Cu wiring is used for the first wiring164. This embodiment is not limited to the above example. Alternatively,an Al wiring can be applied in the same way.

The CMOS inverter may be coupled to the semiconductor elements (forexample, transistors 121 and 122) over the semiconductor substrate 101,for example, via the second wiring 188, the via 189, the first wiring164, the via 162, the wiring 144, and the contact 142. By turning on theCMOS inverter, the semiconductor elements over the semiconductorsubstrate 101 can achieve different functions to each other using thesemiconductor substrate without changing the layout of the semiconductorelements.

Next, a manufacturing method of the semiconductor device in thisembodiment will be specifically described below. FIGS. 3A to 3M showcross-sectional views of the manufacturing method of the semiconductordevice in this embodiment. Each of FIGS. 3A to 3M corresponds to thecross section taken along the line A-A′ of FIG. 2. FIGS. 3A to 3M omitthe illustration of the semiconductor substrate 101, the contact layer130, and the wiring layer 140.

As shown in FIG. 3A, first, the cap insulating layer 171 serving as thefirst gate insulating film (171) and the second gate insulating film(171) is formed in contact with the first gate electrode 210 and thesecond gate electrode 310 over the first wiring layer 150 with the firstwiring including the first gate electrode 210 and the second gateelectrode 310 formed thereover. Then, as shown in FIGS. 3B to 3D, afirst laminated structure (230+232) of the first oxide semiconductorlayer 230 of the first conductive type and the first hard mask layer 232is formed over the first gate electrode 210 via the cap insulating layer171. Subsequently, as shown in FIG. 3E, an insulating film (240) isformed to cover the first laminated structure (230+232) and the capinsulating film 171. Thereafter, as shown in FIG. 3F, the insulatingfilm (240) is etched back to form the first sidewall film 240 coveringeach side of the first oxide semiconductor layer 230. Then, a secondlaminated structure (330+332) of the second hard mask layer 332 and thesecond oxide semiconductor layer 330 of the second conductive type otherthan the first conductive type is formed over the second gate electrode310 via the cap insulating layer 171. Subsequently, the interlayerinsulating film (172) is formed to cover the first laminated structure(230+232) and the second laminated structure (330+332). Thereafter, thesource and drain electrodes (289 and 389) are formed to be coupled tothe respective first oxide semiconductor layer 230 and second oxidesemiconductor layer 330 via the interlayer insulating layer 172, thefirst hard mask 232, and the second hard mask 332.

In this embodiment, as shown in the steps of FIGS. 3E and 3F, thesidewalls 240 are formed over the sides of the first transistor 200 andthe first hard mask 232. The sidewall 240 covers each side of theexposed first oxide semiconductor layer 230, which isolates the firstoxide semiconductor layer 230 from the second oxide semiconductor layer330 physically, chemically, and electrically. Such a function of thesidewall 240 as the element isolation film can prevent the modificationand degradation of the first oxide semiconductor layer 230 due to thepresence of the second oxide semiconductor layer 330 in the previous andfollowing steps.

Additionally, in this embodiment, the above element isolation film isformed not of a coated insulating film itself (to be described later)covering the entire first laminated structure (230+232) but thesidewalls 240 formed by etching back the coated insulating film. Thus,after the “element isolation step”, there is no difference in thicknessof the combination of the hard mask and the coated insulating filmbetween a part located on the first oxide semiconductor layer 230 and apart located on the second oxide semiconductor layer 330. This cansuppress the excessive etching of one of the part over the first oxidesemiconductor layer 230 and the part over the second oxide semiconductorlayer 330 in dry etching for formation of the contact holes, whicheliminates the case where one oxide semiconductor layer is removed as awhole. As a result, this embodiment can result in preventing thedecrease in yield of the formation of the CMOS including the activeelements in the wiring layers due to a contact defect.

Now, the manufacturing method of the semiconductor device 100 in thisembodiment will be further described below.

First, as shown in FIG. 2, the element isolation layer 120 is formed atthe semiconductor substrate 101. Then, the semiconductor elements, forexample, the transistors 121 and 122 are formed over the semiconductorsubstrate 101. Subsequently, the contact layer 130 (including theinterlayer insulating layer 131 and the contact 142), and the wiringlayer 140 (including the interlayer insulating layer 132 and the wiring144) are formed. The related-art methods can be used in these steps.

Then, as shown in FIG. 3A, the cap insulating layer 151 for preventionof the Cu diffusion, and the first interlayer insulating layer 152 aredeposited over the wiring layer 140 (not shown) in that order. Suitablematerials for the cap insulating layer 151 include a silicon nitride(SiN) and silicon carbon nitride (SiCN). The first interlayer insulatinglayer 152 is a low-dielectric insulating layer made of silicon oxide(SiO₂) or material having a dielectric constant lower than that ofsilicon oxide. The first interlayer insulating layer can be acarbon-containing film, such as a SiOC(H) film or a SiLK (registeredtrademark). Subsequently, the via 162, the first wiring 164, the firstgate electrode 210, and the second gate electrode 310 are embedded inthe first interlayer insulating layer 152 by a single damascene methodor a dual damascene method. In this way, the first wiring layer 150 isformed. Suitable materials for the via 162, the first wiring 164, thefirst gate electrode 210, and the second gate electrode 310 can include,for example, copper (Cu). Therefore, the cap insulating layer 171 isformed to cover the first interlayer insulating layer 152, the firstwiring 164, the first gate electrode 210, and the second gate electrode310. Suitable materials for the cap insulating layer 171 include asilicon nitride (SiN) and silicon carbon nitride (SiCN). The capinsulating layer 171 has a thickness of about 10 to 50 nm. These stepsare performed in the same way as that of the normal semiconductor devicewith a copper (Cu) wiring layer.

Then, as shown in FIG. 3B, the first oxide semiconductor layer 230serving as the channel of the first transistor 200 is formed over thecap insulating layer 171, for example, by sputtering. Suitable materialsfor the channel include an InGaZnO(IGZO) layer, an InZnO layer, a ZnOlayer, a ZnAlO layer, a ZnCuO layer, a NiO layer, a SnO layer, a SnO₂layer, a CuO layer, a Cu₂O layer, a Ta₂O₅ layer, and a TiO₂ layer. Thefirst oxide semiconductor layer 230 has a thickness of about 10 to 50nm. Subsequently, the first hard mask 232 is formed over the first oxidesemiconductor layer 230, for example, by a plasma CVD method. The firsthard mask 232 is an insulating film made of silicon oxide (SiO₂),silicon oxycarbide (SiOC), carbon (C), or silicon nitride (SiN), or acombination thereof. The first hard mask 232 preferably has a thicknessof about 30 to 200 nm.

Then, as shown in FIG. 3C, the first oxide semiconductor layer 230 andthe first hard mask 232 are patterned using the normal photolithographyand dry etching. Thus, the first oxide semiconductor layer 230 and thefirst hard mask 232 are formed into the element shape of the firsttransistor 200. That is, the first oxide semiconductor layer 230 servingas the channel for the first transistor 200 is shaped in the form ofisland (see FIG. 2). Then, as shown in FIG. 3D, a resist over the firsthard mask 232 is removed. As a result, the cap insulating layer 171 andthe first hard mask 232 are exposed over the surface, and further thesides of the island-shaped first oxide semiconductor layer 230 under thefirst hard mask 232 are also exposed.

Then, as shown in FIG. 3E, the insulating film (hereinafter referred toas the coated insulating film 240) serving as the sidewalls 240 isformed over the cap insulating layer 171 and the first hard mask 232,for example, by the CVD method. Suitable materials for the coatedinsulating film 240 (insulating film serving as the sidewall 240)include silicon oxide (SiO₂), and silicon nitride (SiN). The insulatingfilm 240 has a thickness of about 10 to 200 nm. The coated insulatingfilm 240 covers not only the surfaces of the cap insulating layer 171and the first hard mask 232, but also the exposed sides of the firstoxide semiconductor layer 230.

Then, as shown in FIG. 3F, the entire coated insulating film 240 isetched back. Thus, the sidewalls 240 are formed over the sides of thefirst oxide semiconductor layer 230 and the first hard mask 232. Eachsidewall 240 covers the exposed side of the island-shaped first oxidesemiconductor layer 230 to protect the side from influences of otherfilms and processes. Taking into consideration the role of the sidewall240, the sidewall 240 has only to cover at least the sidewall of thefirst oxide semiconductor layer 230 even when the sidewall 240 does notcover the side of the first hard mask 232. As shown in FIG. 3L, when thethickness of the part etched back is decreased for safety to form thesidewall 240 over the sides of the first oxide semiconductor layer 230and the first hard mask 232, the coated insulating film 240 may remainslightly above the cap insulating layer 171 and the first hard mask 232.

Then, as shown in FIG. 3G, the second oxide semiconductor layer 330serving as the channel of the second transistor 300 is formed over thecap insulating layer 171, the first hard mask 232, and the sidewalls240, for example, by the sputtering. Suitable materials for the channelinclude an InGaZnO(IGZO) layer, an InZnO layer, a ZnO layer, a ZnAlOlayer, a ZnCuO layer, a NiO layer, a SnO layer, a SnO₂ layer, a CuOlayer, a Cu₂O layer, a Ta₂O₅ layer, and a TiO₂ layer. The second oxidesemiconductor layer 330 has a thickness of about 10 to 50 nm.Subsequently, the second hard mask 332 is formed over the second oxidesemiconductor layer 330, for example, by the plasma CVD method. Thesecond hard mask 332 is an insulating film made of silicon oxide (SiO₂),silicon oxycarbide (SiOC), carbon (C), or silicon nitride (SiN), or acombination thereof. The second hard mask 332 has a thickness of about30 to 200 nm.

Then, as shown in FIG. 3H, the second oxide semiconductor layer 330 andthe second hard mask 332 are patterned using the normal photolithographyand dry etching. The second oxide semiconductor layer 330 and the secondhard mask 332 are formed in the shape corresponding to the element shapeof the second transistor 300. That is, the second oxide semiconductorlayer 330 serving as a channel for the second transistor 300 is shapedin the form of island (see FIG. 2). Then, as shown in FIG. 3I, a resistover the second hard mask 332 is removed. The first transistor 200including the first hard mask 232, the first oxide semiconductor layer230, and the sidewalls 240, and the second transistor 300 including thesecond hard mask 332 and the second oxide semiconductor layer 330 areformed over the cap insulating layer 171.

Then, as shown in FIG. 3J, the second interlayer insulating layer 172 isformed to cover the cap insulating layer 171, the first hard mask 232,the sidewalls 240, and the second hard mask 332. The second interlayerinsulating layer 172 is a low-dielectric insulating layer made ofsilicon oxide (SiO₂) or material having a dielectric constant lower thanthat of silicon oxide. The second interlayer insulating layer 172 can bea carbon-containing film, such as a SiOC(H) film or a SiLK (registeredtrademark). Substantially, as shown in FIG. 3K, the via 189, thecontacts (source/drain electrode) 289 and 389, and the second wirings188, 288, and 388 are embedded in the second interlayer insulating layer172 by the single damascene method or dual damascene method. Thus, thesecond wiring layer 170 is formed. Suitable materials for the via 189,the contacts 289 and 389, and the second wirings 188, 288, and 388include copper (Cu) using a titanium (Ti)/titanium nitride (TiN) orTa/TaN as a barrier film. Although not shown in the figure, the secondinterlayer insulating layer 172 may use a pad electrode comprised ofTiN/Al/TiN/Ti which is formed over the second interlayer insulatinglayer 172 embedded in the formed via.

In the above steps, the semiconductor device 100 according to thisembodiment is manufactured.

As shown in FIG. 3L instead of FIG. 3F, when the coated insulating film240 slightly remains over the cap insulating layer 171 and the firsthard mask 232 upon forming the sidewalls 240 on the sides of the firstoxide semiconductor layer 230 and the first hard mask 232, thesemiconductor device 100 finally takes the structure shown in FIG. 3Mand not in FIG. 3K.

In the steps shown in FIGS. 3E and 3F of the manufacturing method of thesemiconductor device in this embodiment, the sidewalls 240 are formedover the sides of the first oxide semiconductor layer 230 and the firsthard mask 232. However, another manufacturing method of a semiconductordevice without forming the sidewalls 240 can also be proposed. Forexample, the following method can be used.

FIGS. 4A and 4B show cross-sectional views of (a part of) themanufacturing method of the semiconductor device without forming thesidewalls 240. As shown in FIG. 4A, directly after the step shown inFIG. 3D, the second oxide semiconductor layer 330 and the second hardmask 332 are deposited over the cap insulating layer 171, the firstoxide semiconductor layer 230, and the first hard mask 232 in thatorder. Then, as shown in FIG. 4B, the second oxide semiconductor layer330 and the second hard mask 332 are patterned using normalphotolithography and dry etching. Thereafter, the same steps as thoseshown in FIGS. 3J and 3K are performed.

The above manufacturing method using the steps of FIGS. 4A and 4B aresimplified by omitting the steps shown in FIGS. 3E and 3F. However, upondepositing the second oxide semiconductor layer 330, parts of the sidesof the first oxide semiconductor layer 230 under the first hard mask 232are exposed (see P1 of FIG. 4A). Thus, the second oxide semiconductorlayer 330 is in contact with the sides of the first oxide semiconductorlayer 230. As a result, the material of the second oxide semiconductorlayer 330 might be diffused into the first oxide semiconductor layer230. Alternatively, the material of the first oxide semiconductor layer230 might be diffused into the second oxide semiconductor layer 330.Otherwise, etching residues might generate a region where the N-type andP-type semiconductor areas are in contact with each other, whichpossibly modifies and degrades the properties of the first oxidesemiconductor layer 230.

In this embodiment, in the steps shown in FIGS. 3E and 3F, the sidewalls240 are formed over the sides of the cap insulating layer 171 and thefirst hard mask 232. Each sidewall 240 covers the exposed side of thefirst oxide semiconductor layer 230 to separate the first oxidesemiconductor layer 230 from other films (for example, second oxidesemiconductor layer 330) physically, chemically, and electrically. Thus,the function of the sidewall 240 as the element isolation film canprevent the modification and degradation of the properties of the firstoxide semiconductor layer 230.

In the steps shown in FIGS. 3E and 3F of the manufacturing method of thesemiconductor device in this embodiment, the coated insulating film 240is formed over the cap insulating layer 171 and the first hard mask 232,and etched back to thereby form the sidewalls 240. However, anothermanufacturing method of a semiconductor device can also be proposedwhich involves maintaining the coated insulating film 240 as it iswithout etching back. For example, the following method can be used.

FIGS. 5A to 5D show cross-sectional views of (a part of) themanufacturing method of the semiconductor device with the coatedinsulating film for the sidewall remaining. Directly after the stepshown in FIG. 5A (which is the same as that of FIG. 3E), as shown inFIG. 5B, the second oxide semiconductor layer 330 and the second hardmask 332 are deposited over the coated insulating film 240 in that orderwithout performing the etching back. Then, as shown in FIG. 5C, thesecond oxide semiconductor layer 330 and the second hard mask 332 arepatterned using the normal photolithography and dry etching. Then, asshown in FIG. 5D, the second interlayer insulating layer 172 is formedto cover the coated insulating film 240 and the second hard mask 332, sothat the via 189, the contacts 289 and 389, and the second wirings 188,288, and 388 are embedded in the second interlayer insulating layer 172by the single damascene method or dual damascene method.

The above manufacturing method using the steps of FIGS. 5A to 5D aresimplified by omitting the step shown in FIG. 3F. Additionally, upondepositing the second oxide semiconductor layer 330, the sides of thefirst oxide semiconductor layer 230 under the first hard mask 232 arecovered with the coated insulating film 240, which can prevent themodification and degradation of the properties of the first oxidesemiconductor layer 230 which might be caused in the steps of FIGS. 4Aand 4B in the related art (see P2 of FIG. 5B). That is, the coatedinsulating film 240 plays the role of the element isolation film. Themanufacturing method, however, has the following problems.

Then, as shown in FIG. 5D, a laminated structure (having a thickness d1)of the first hard mask 232 and the coated insulating film 240 is formedover the first oxide semiconductor layer 230. In contrast, only thesecond hard mask 332 (having a thickness d2) is formed over the secondoxide semiconductor layer 330. This causes a difference in thickness ofthe insulating film over the oxide semiconductor layer between the firsttransistor 200 and the second transistor 300 (Δd1=d1−d2). When formingthe contact holes, including the contacts 289 and 389, by etching, sucha difference in thickness Δd1 might make it impossible to perform theappropriate etching. For example, when etching is intended to beperformed to match the depth of the contact hole for the contact 289, anetched part might penetrate the second oxide semiconductor layer 330through the contact hole of the contact 389. Further, when etching isintended to be performed to match the depth of the contact hole for thecontact 389, the contact hole including the contact 289 cannot be dugsufficiently, and an etched part might not reach the first oxidesemiconductor layer 230.

At the same time, as shown in FIG. 5D, the gate insulating film of thefirst transistor 200 is only the cap insulating film 171 (having athickness d3). In contrast, the gate insulating film of the secondtransistor 300 includes a laminated structure (having a thickness d4) ofthe cap insulating layer 171 and the coated insulating film 240. Thiscauses a difference in thickness of the gate insulating film between thefirst transistor 200 and the second transistor 300 (Δd2=d4−d3). In useof the first transistor 200 and the second transistor 300 as the CMOSinverter, such a difference in thickness Δd2 might make it almostimpossible to appropriately perform on-off operations.

The differences in film thickness Δd1 and Δd2 are caused depending onwhether the coated insulating film 240 exists above the oxidesemiconductor layer (channel) or under the layer as shown in FIG. 5D.The difference in thickness Δd2 between the gate insulating films can beextinguished by another manufacturing method of a modified example ofthis embodiment to be described later and the like. This method enablesselection of the gate insulating film optimized for the conductive typesof the respective oxide semiconductors. In contrast, the difference inthickness Δd1 between the insulating films over the oxide semiconductorlayer is difficult to extinguish.

However, the manufacturing method of the semiconductor device accordingto this embodiment can solve the problems.

FIG. 6 is a table showing the difference between the structure shown inFIG. 5D and the structure of this embodiment. The column “B” indicatesthe structure shown in FIG. 5D, and the column “A” indicates thestructure of this embodiment. The column “NMOS” indicates the thicknessof the insulating layer over the first oxide semiconductor layer 230.The column “PMOS” indicates the thickness of the insulating layer overthe second oxide semiconductor layer 330. The row “NMOS-HM” indicatesthe time of formation of the first hard mask 232. The row “NMOS PROCESS”indicates the time of processing the first hard mask 232 into the shapeof a channel. The row “ELEMENT ISOLATION” indicates the time offormation of the coating insulating film 240, or formation of thesidewalls 240 by etching back in the following step. The row “PMOS-HM”indicates the time of formation of the second hard mask 332. The row“PMOS PROCESS” indicates the time of processing the second hard mask 332into the shape of a channel. The row “ILD DEPOSITION” indicates the timeof formation of an interlayer insulating layer 1720.

In the structure (“B”) shown in FIG. 5D, a laminated structure of aremaining film (of 60 nm in thickness) of the hard mask (HM) obtainedafter the process, and the coated insulating film 240 (of 50 nm inthickness) for element isolation remains in the first transistor 200(“NMOS”) previously formed. As a result, the thickness of the film overthe first oxide semiconductor 230 becomes 110 nm (“ELEMENT ISOLATION”).Thereafter, the remaining film (of 60 nm in thickness) of the hard mask(HM) obtained after the process remains at the formed second transistor300 (“PMOS”). As a result, the thickness of the film over the secondoxide semiconductor 330 becomes 60 nm (“PMOS PROCESS”). This results ina difference in thickness Δd (in the example of this Table, 50 nm)between the part located over the first oxide semiconductor layer 230and the part located over the second oxide semiconductor layer 330. Thismight lead to the excessive etching of the upper part of the secondoxide semiconductor layer 330 (over the PMOS) when the dry etching timefor formation of the contact hole is set to the time required to etchthe part over the first oxide semiconductor layer 230 (over the NMOS).

In the structure (“A”) of this embodiment, the element isolation isachieved not by the coated insulating film 240 itself, but by thesidewalls 240 formed by etching back the coated insulating film 240.Also, after the “element isolation”, there is no difference between thepart over the first oxide semiconductor layer 230 and the part over thesecond oxide semiconductor layer 330. As a result, the dry etching timefor formation of the contact hole can be set to the same value betweenthe etching of the part located over the first oxide semiconductor layer230 and the etching of the part located over the second oxidesemiconductor layer 330. Thus, there is no case where one oxidesemiconductor layer (on the PMOS side in the example of the table) isentirely extinguished (that is, where the contact hole completelypenetrates the oxide semiconductor layer). As a result, this embodimentcan prevent the decrease in yield of the semiconductor device due tocontact defects in the formation of the CMOS including the activeelements in the wiring layer.

First Modified Example

FIG. 7 shows a cross-sectional view of a first modified example of thestructure of the semiconductor device in this embodiment. The case shownin FIG. 7 differs from the case shown in FIG. 1A in not only that thesidewalls 240 are formed over the sides of the first hard mask 232 andthe first oxide layer 230, but also that sidewalls 340 are formed overthe sides of the second hard mask 332 and the second oxide semiconductorlayer 330. The differences will be mainly described below.

In order to obtain such a structure, in the manufacturing method of thesemiconductor device shown in FIGS. 3A to 3K, the following steps may beinserted into between the steps shown in FIGS. 3I and 3J. First, in thesame way as the step shown in FIG. 3E, the insulating film serving asthe sidewall 340 is formed over the cap insulating layer 171, the firsthard mask 232, the sidewalls 240, and the second hard mask 332, forexample, by the CVD method. Then, in the same way as the step shown inFIG. 3F, the entire insulating film serving as the sidewall 340 isetched back. Thus, the sidewalls 340 are formed over the sides of thesecond oxide semiconductor layer 330 and the second hard mask 332. Inthis case, a sidewall 241 sometimes remains over the side of thesidewall 240.

The modified example can also provide the same effects as thoseexhibited in the cases shown in FIGS. 1A, 1B, and 2. Further, eachsidewall 340 covers the exposed side of the second oxide semiconductorlayer 330. Thus, the sidewalls 340 can protect the second oxidesemiconductor layer 330 against influences from other films orprocesses.

Second Modified Example

FIG. 8 shows a cross-sectional view of a second modified example of thestructure of the semiconductor device in this embodiment. The case shownin FIG. 8 differs from the case shown in FIG. 1 in that the thickness ofthe cap insulating layer 171 differs between in the position of thefirst transistor 200 and in the position of the second transistor 300.Now, the differences will be mainly described.

The cap insulating layer 171 for preventing diffusion of Cu is thinnerin a region without the first oxide semiconductor layer 230 than that inanother region with the first oxide semiconductor layer 230 by adifference in thickness Δd. Such a structure is very useful when adifference in thickness of the gate insulating film between the firsttransistor 200 and the second transistor 300 is required due to thedifference in material properties between the first oxide semiconductorlayer 230 and the second oxide semiconductor layer 330.

FIGS. 9A and 9B show cross-sectional views of a manufacturing method (apart thereof) of the second modified example of the semiconductor devicein the first embodiment. After the step shown in FIG. 3E, as shown inFIG. 9A (which is the same as the step shown in FIG. 3F), the sidewalls240 are formed over the sides of the first oxide semiconductor layer 230and the first hard mask 232, and then as shown in FIG. 9B, over-etchingis performed for an adequate over etching time. Thus, the cap insulatingfilm 171 can be selectively thinned in the region without the firstoxide semiconductor layer 230. The following steps are the same as thoseafter the step shown in FIG. 3G. The over-etching at this time canadjust the thickness of the first hard mask 23 by etching back theentire surface.

The modified example can also provide the same effects as thoseexhibited in the cases shown in FIGS. 1A, 1B, and 2.

This can cause a difference in thickness of the gate insulating filmbetween the first transistor 200 and the second transistor 300.

Second Embodiment

The structure of a semiconductor device according to a second embodimentof the invention will be described below. FIG. 10 shows across-sectional view of the semiconductor device structure in thisembodiment. The semiconductor device of this embodiment differs from thesemiconductor device of the first embodiment, especially the secondmodified example of the first embodiment (see FIGS. 8, 9A and 9B) inthat a gate insulating film of the second transistor 300 has adouble-layered structure. The differences will be mainly describedbelow.

The cap insulating layer 171 for preventing the diffusion of Cu isthinned in a region without the first oxide semiconductor layer 230 by adifference Δd in thickness of the layer as compared to in a region withthe first oxide semiconductor layer 230 like the second modified exampleof the first embodiment. In this embodiment, however, a second uppergate insulating film 320 is formed between the thinned cap insulatinglayer 171 and the second oxide semiconductor layer 330. Thus, forexample, even in the over-etching of the gate insulating film (171) ofthe first transistor 200 as shown in FIG. 9B, the gate insulating filmof the first transistor 200 can have substantially the same thickness asthat of the gate insulating film of the second transistor 300. Forexample, the gate insulating film of the second transistor 300 can beformed of the desired material (for example, high-k film) in the desiredthickness.

Such a structure can be achieved by the following steps. First, afterthe step shown in FIG. 9B of the second modified example of the firstembodiment, and before the step shown in FIG. 3G (formation of thesecond oxide semiconductor layer 330), the second upper gate insulatingfilm 320 is formed. Suitable materials for the second upper gateinsulating film 320 include, for example, silicon oxide (SiO₂), siliconnitride (SiN), and aluminum oxide (AlOx). Subsequently, in the stepshown in FIG. 3G, the second oxide semiconductor layer 330 and thesecond hard mask 332 are formed above the second upper gate insulatingfilm 320 in that order. In the steps shown in FIGS. 3H and 3I, thesecond transistor 300 is patterned in the form of a channel with respectto the second upper gate insulating film 320, the second oxidesemiconductor layer 330, and the second hard mask 332. At that time, thesecond upper gate insulating film 320 is also processed in the sameshape. Alternatively, the second upper gate insulating film 320 may notbe patterned and may remain substantially on the front side. Thefollowing steps are the same as the steps shown in FIGS. 3J and 3K.

This embodiment can also provide the same effects as those exhibited inthe first embodiment. By providing the second upper gate insulating film320 under the second oxide semiconductor layer 330, each of the firstoxide semiconductor layer 230 and the second oxide semiconductor layer330 can have the corresponding optical (desired) gate insulating film.This can achieve the reduction in gate leakage, the control of athreshold of the transistor, and the improvement of reliability of thetransistor. Especially, the second transistor 300 can have the optimizedmaterial and thickness.

Third Embodiment

The structure of a semiconductor device according to a third embodimentwill be described below. FIG. 11 shows a cross-sectional view of thesemiconductor device structure in this embodiment. The semiconductordevice of this embodiment differs from the semiconductor device of thefirst embodiment in that both the gate insulating film of the firsttransistor 200 and the gate insulating film of the second transistor 300have the double-layered structure. Now, the differences will be mainlydescribed.

The cap insulating layer 171 for preventing the diffusion of Cu isformed over the first wiring layer 150 to have the uniform thickness.However, the second upper gate insulating film 220 is formed under thefirst oxide semiconductor layer 230, and the second upper gateinsulating film 320 is formed under the second oxide semiconductor layer330. Thus, for example, each of the gate insulating film of the firsttransistor 200 and the gate insulating film of the second transistor 300can be formed of the desired material in the desired thickness. That is,the respective gate insulating films can be individually optimized.

Such a structure can be achieved by the following steps. First, afterthe step shown in FIG. 3A of the first embodiment, and before the stepshown in FIG. 3B (formation of the first oxide semiconductor layer 230),the first upper gate insulating film 220 is formed. Subsequently, in thesteps shown in FIGS. 3B to 3D, in patterning the first oxidesemiconductor layer 230 and the first hard mask 232, the first uppergate insulating film 220 is processed into the same shape. Then, afterthe steps shown in FIGS. 3E and 3F, and before the step shown in FIG. 3G(formation of the second oxide semiconductor layer 330), the secondupper gate insulating film 320 is formed. Then, in the steps shown inFIGS. 3G to 3I, in patterning the second oxide semiconductor layer 330and the second hard mask 332, the second upper gate insulating film 320is also processed into the same shape. The following steps are the sameas the steps shown in FIGS. 3J and 3K.

This embodiment can also provide the same effects as those exhibited inthe first embodiment.

The first upper gate insulating film 220 is disposed under the firstoxide semiconductor layer 230, and the second upper gate insulating film320 is disposed under the second oxide semiconductor layer 330, wherebyeach of the first oxide semiconductor layer 230 and the second oxidesemiconductor layer 330 can have the optical (desired) gate insulatingfilm. This can achieve the reduction in gate leakage, the control of athreshold of the transistor, and the improvement of reliability of thetransistor. In particular, the materials and thicknesses of the firsttransistor 200 and the second transistor 300 can be respectivelyoptimized.

Fourth Embodiment

The structure of a semiconductor device according to a fourth embodimentwill be described below. FIG. 12 shows a cross-sectional view of thesemiconductor device structure in this embodiment. The semiconductordevice of this embodiment differs from the semiconductor device of thethird embodiment in that the shape of the gate insulating film of eachof the first transistor 200 and the second transistor 300 is larger thanthat of the oxide semiconductor layer in the planar view. Now, thedifferences will be mainly described.

The cap insulating layer 171 for preventing the diffusion of Cu isformed over the first wiring layer 150 to have the uniform thickness. Incontrast, the sidewalls 240 are formed not only over the sides of thefirst oxide semiconductor layer 230 and the first hard mask 232, butalso over the sides of the second oxide semiconductor layer 330 and thesecond hard mask 332. The first upper gate insulating film 220 is formedunder the first oxide semiconductor layer 230 and the sidewalls 240surrounding the semiconductor layer to have a shape that matches theshapes of the semiconductor layer 230 and the sidewalls 240. Likewise,the second upper gate insulating film 320 is formed under the secondoxide semiconductor layer 330 and the sidewalls 340 surrounding thesemiconductor layer to have a shape that matches the shapes of thesemiconductor layer 330 and the sidewalls 340.

Such a structure can be achieved by the following steps. FIGS. 13A to13C show cross-sectional views of the manufacturing method (a partthereof) of the semiconductor device according to the third embodiment.First, after the step shown in FIG. 3A of the first embodiment, andbefore the step shown in FIG. 3B (formation of the second oxidesemiconductor layer 230), the first upper gate insulating film 220 isformed. Subsequently, in the steps shown in FIGS. 3B to 3D, inpatterning the first oxide semiconductor layer 230 and the first hardmask 232, the first upper gate insulating film 220 is not processed (seeFIG. 13A). Then, after the steps shown in FIGS. 3E and 3F (FIG. 13B),and before the step shown in FIG. 3G (formation of the second oxidesemiconductor layer 330), the first upper gate insulating film 220 isetched into the same shape as the first hard mask 232 and the sidewalls240 (see FIG. 13C). Thus, an island-shaped laminated structure is formedon the first transistor 200 side. Then, the second upper gate insulatingfilm 320 is formed to cover the laminated structure and the capinsulating layer 171. Subsequently, in the steps shown in FIGS. 3G to3I, in patterning the second oxide semiconductor layer 330 and thesecond hard mask 332, the second upper gate insulating film 320 is notprocessed. After the step shown in FIG. 3I and before the step shown inFIG. 3J (formation of the second interlayer insulating layer 172), inthe same way as the step shown in FIG. 3E, the insulating film servingas the sidewall 340 is formed over the second upper gate insulating film320 and the second hard mask 332, for example, by the CVD method. Then,the entire insulating film serving as the sidewall 340 is etched back inthe same way as the step shown in FIG. 3F. Thus, the sidewalls 340 areformed over the sides of the second oxide semiconductor layer 330 andthe second hard mask 332 (in this case, the sidewalls 241 often remainover the sides of the sidewall 240). Thereafter, the second upper gateinsulating film 320 is etched into the shape of the second hard mask 332and the sidewall 340. Thus, an inland-shaped laminated structure isformed on the second transistor 300 side. The following steps are thesame as the steps shown in FIGS. 3J and 3K.

This embodiment can also provide the same effects as those exhibited inthe third embodiment.

Additionally, the gate insulating film (of two layers) can be set widerthan the channel (oxide semiconductor layer). The use of the abovestructure can largely reduce the leakage at the end surface of the gateinsulating film, which can manufacture the device with higherreliability.

When only one layer of the cap insulating layer 171 is sufficient toserve as the insulating film under the sidewalls 240 and 340, the hardmasks 232 and 332, the oxide semiconductor layers 230 and 330, and thegate insulating films 220 and 320 may be totally etched at once, andthereafter the sidewalls 240 may be formed.

Fifth Embodiment

The structure of a semiconductor device in a fifth embodiment of theinvention will be described below. FIG. 14 shows a cross-sectional viewof the semiconductor device structure in this embodiment. Thisembodiment relates to a P-type transistor using a P-type oxidesemiconductor layer as a channel. Such a transistor can be used as thetransistor of the semiconductor device in each of the first to fourthembodiments. Further, this embodiment can be applied not only to thetransistor of the semiconductor device, but also widely to electriccoupling between a P-type oxide semiconductor layer and metal andanother electric coupling between a wide bandgap semiconductor and metalin the same way.

FIG. 14 shows an example of a transistor structure as the semiconductordevice of this embodiment. The transistor includes a gate electrode 10,a gate insulating film 20, an oxide semiconductor layer 30, sidewalls40, and source/drain electrodes (contacts) 50. The oxide semiconductorlayer 30 is of the P type. The P-type oxide semiconductor layer 30 is,for example, a ZnO layer, a ZnAlO layer, a ZnCuO layer, a NiO layer, aSnO layer, and a Cu₂O layer, each layer having impurities doped therein.The source/drain electrode 50 may have a double-layered structure asshown in the figure. In that case, the source/drain electrode 50includes a first layer 50 a in contact with the oxide semiconductorlayer 30, and a second layer 50 b provided over the first layer 50 a. Aslong as the source/drain electrode 50 can be in ohmic contact with theoxide semiconductor layer 30, the first layer 50 a may be thin. Suitablematerials for the source/drain electrode 50 will be described later.

When the above transistor is applied to the respective embodiments, thecomponents of the transistor will correspond to the elements of therespective embodiments as follows. The gate electrode 10 corresponds tothe gate electrode 210 or 310. The gate insulating film 20 correspondsto the cap insulating layer 171 (or 171+220, or 171+320). The oxidesemiconductor layer 30 corresponds to the oxide semiconductor layer 230or 330. The sidewall 40 corresponds to the sidewall 240 or 340. Thesource/drain electrode 50 corresponds to the contact 289 or 389. Thisfigure omits the illustration of the hard masks 232 and 332.

In the above first to fourth embodiments, active elements (wiring activeelements) are provided in the wiring layer. In this case, in order toform all or a part of the circuit using the wiring active elements, itis necessary to provide an N-type wiring active element and a P-typewiring active element. The N-type wiring active element can be, forexample a wiring active element using InGaZnO as a channel. The P-typewiring active element can be formed of for example, SnO. In order toachieve the P-type wiring active element, an oxide semiconductor havingP-type conductivity is required but is a wide-gap semiconductor mainlyhaving a band gap of 2 eV or more. In general, the wide-gapsemiconductor has a conduction band end positioned at around 4 eV indepth as viewed from a vacuum level, and a valance band end positionedat 6 to 7.5 eV. In contrast, normal metal has a work function of about3.8 to 5.65 eV. Thus, the contact between P-type wide-gap semiconductorand the metal causes the Schottky barrier. In contrast, the formation ofOhmic contact between the P-type semiconductor and the metal for contactis very important in the P-type field-effect transistor using thewide-gap semiconductor or a device using a P/N junction so as to reducea parasitic resistance of the device.

Patent Documents 2 and 3 disclose a P-type field-effect transistor usinga P-type oxide semiconductor SnO. The transistor includes the P-typeoxide semiconductor SnO formed as a channel over a YSZ substrate, ana-Al₂Ox formed thereover as a gate insulating film, and a metallamination of Ni and Au formed as a source/drain electrode and a gateelectrode. Non-Patent Document 4 discloses a P-type field-effecttransistor using a P-type oxide semiconductor SnO. The transistorincludes a SiNx layer formed as a gate insulating film over an n⁺-typeSi substrate also serving as a gate electrode, a P-type oxidesemiconductor SnO formed thereover as a channel, and a Pt metal formedas a source/drain electrode in contact with the SnO.

The field-effect transistors disclosed in the above Patent Document 2,Non-Patent Document 3, and Non-Patent Document 4 use Ni, Au, or Pt whosework function is more than 5 eV as metal, to reduce a contact resistanceagainst the P-type oxide semiconductor SnO. However, the inventors havefurther studied and just found the following facts. That is, when usingthe above metal as metal for contact with the P-type oxidesemiconductor, a large contact resistance, or a parasitic resistance iscaused between the metal for contact and the P-type oxide semiconductordue to the Schottky barrier, which interrupts the measurement of variousproperties of the P-type semiconductor. Thus, the development andachievement of the material and process for minimizing the contactresistance between the contact metal and the P-type oxide semiconductorbecomes an important issue.

In this embodiment, the contact metal coupling to the P-type oxidesemiconductor layer 30 is formed of a conductive oxide. That is, amaterial for at least the first layer 50 a of the source/drain electrode50 for use is a conductive oxide. The conductive oxide has a valanceband positioned in the substantially same position as the valance bandof the P-type oxide semiconductor, which is preferable for forming anOhmic contact. This arrangement can reduce the contact resistance to theP-type oxide semiconductor. Material for the second layer 50 b may bethe same as that of the first layer 50 a, or may be other conductiveoxides or metal to make the Ohmic contact with the first layer 50 a.

Suitable materials for the conductive oxide as the contact metalinclude, for example, indium oxide (ITO), ruthenium oxide (RuO₂),titanium oxide (TiOx), an oxygen-deficient oxide semiconductor, an oxidesemiconductor doped with metal, and the like. The oxide semiconductorsin this case can be used as the channel, and include various kinds ofoxide semiconductors with different degrees of oxygen deficiency, withdifferent kinds of metals, or with different degrees of doping. Theoxide semiconductor preferably has a valance band deeper than that ofthe P-type oxide semiconductor, and more preferably deeper than that ofthe oxide semiconductor 30.

Material for contact with the N-type oxide semiconductor for use can bemetal and not the above conductive oxide. Thus, in the circuit (forexample, of the first to fourth embodiments) using both the N-typewiring active element and the P-type wiring active element, the N-typeand P-type wiring active elements use different materials for contact.

In manufacturing the semiconductor device of this embodiment, thefollowing method will be proposed. That is, in manufacturing the circuitusing both the N-type wiring active element and the P-type wiring activeelement, separated production processes are introduced for formation ofthe contacts. Specifically, for example, in the first to fourthembodiments, in the step shown in FIG. 3K, an N-type oxide semiconductorlayer side is subjected to masking by a hard mask upon forming thesource/drain electrode in the P-type oxide semiconductor layer.Likewise, a P-type oxide semiconductor layer side is subjected tomasking by a hard mask upon forming the source/drain electrode in theN-type oxide semiconductor layer. In use of a laminated structure of thefirst layer 50 a and the second layer 50 b as the source/drain electrode50, a laminated film including a film for the first layer 50 a andanother film for the second layer 50 b is formed.

FIG. 15 is a graph showing the characteristics of contact between thecontact material and the oxide semiconductor layer. In the figure, alongitudinal axis indicates a current flowing between the contactmaterial and the oxide semiconductor layer (for example, SnO), and ahorizontal axis indicates a voltage between the contact material and theoxide semiconductor layer. As shown in the figure, when using gold (Au)as the material for contact, the current is proportional to the voltage,but the contact resistance is so large that the current is low. This isdue to the influence of the Schottky barrier. In contrast, when usingruthenium oxide (RuO₂) as the contact material, which is one of theconductive oxides, the current is proportional to the voltage. Ascompared to the use of Au, the contact resistance is small, and thecurrent is large at the same voltage. That is, the use of the rutheniumoxide can exhibit good Ohmic contact whose contact resistance is small.In this case, one layer of ruthenium oxide (RuO₂) is used as thesource/drain electrode 50.

The structure of this embodiment uses the conductive oxide for formationof contact to the P-type oxide semiconductor layer 30, which can alignthe valance band by the band structure of the oxides. Thus, thisembodiment can form the Ohmic contact with the P-type oxidesemiconductor layer. Such a conductive oxide can be applied to thewide-gap semiconductor (for example, GaN, SiC) having a band gap of 2 eVor more.

Sixth Embodiment

The structure of a semiconductor device in a sixth embodiment of theinvention will be described below. FIG. 16 shows a cross-sectional viewof the semiconductor device structure in this embodiment. Thesemiconductor device of this embodiment differs from the semiconductordevice of the fifth embodiment in the use of an interface layer 50 c asthe source/drain electrode (contact). Now, the differences will bemainly described.

In this embodiment, as the material for the source/drain electrode 50(at least first layer 50 a) is the material for forming an interfacelayer 50 c with respect to the oxide semiconductor of the oxidesemiconductor layer 30. The material can include metal, such as titanium(Ti). When such a material is used to form the source/drain electrode(contact), the interface layer 50 c that can reduce the Schottkey effector can form the Ohmic contact is formed at an interface between thesource/drain electrode 50 and the oxide semiconductor layer 30. Thisembodiment can achieve the reduction in contact resistance to the P-typeoxide semiconductor layer 30.

For example, the contact of the above material (for example, metal, suchas Ti) with the P-type oxide semiconductor (for example, SnO) will causethe following phenomena. At the contacting part, the material pulls asmall amount of oxygen from the oxide semiconductor, and slightlyreduces the oxide semiconductor. As a result, a modified metal layer(metallic layer) is formed (for example, of Sn) on the oxidesemiconductor side by reduction. In contrast, on the material side, ametal oxide layer (for example, TiOx) is formed by the oxidation of thepulled oxygen. Such an interface structure causes a mechanism, forexample, suppresses the depletion of the oxide semiconductor to reduceband vending, which reduces the Schottky effect. Thus, such a materialis suitable for forming the Ohmic contact. In this case, the interfacelayer 50 c can be regarded as the interface structure including both themodified metal layer and the metal oxide layer.

That is, the interface layer 50 c can be regarded as the layer formed byreaction between the material of the source/drain electrode and thematerial of the oxide semiconductor layer. Specifically, for example,the interface layer 50 c can also be regarded as the layer formed bydiffusing one or both of a part of elements of the material of thesource/drain electrode and a part of elements of the material of theoxide semiconductor to each other to partly modify the source/drainelectrode or the oxide semiconductor. Alternatively, the interface layer50 may be regarded as a gradational layer whose composition graduallychanges. The interface layer 50 c may be positioned on the source/drainelectrode side, or on the oxide semiconductor side, or on both sidesthereof.

The semiconductor device of this embodiment can be manufactured by thesame method as in the fifth embodiment. In this case, material forforming the interface layer 50 c with respect to the above oxidesemiconductor can be used as the material for contact. If necessary,heat treatment or the like may be performed to promote the formation ofthe interface layer 50.

FIG. 17 is a graph showing the characteristics of contact between thecontact material and the oxide semiconductor layer. In the figure, alongitudinal axis indicates a current flowing between the contactmaterial and the oxide semiconductor layer (for example, SnO), and ahorizontal axis indicates a voltage between the contact material and theoxide semiconductor layer. As shown in the figure, when using gold (Au)as the material for contact, the current is proportional to the voltage,but the contact resistance is so large that the current is low. This isdue to the influence of the Schottky barrier. In contrast, when usingtitanium (Ti)/ruthenium oxide (RuO₂), which is one of the conductiveoxides, as the contact material, the current is proportional to thevoltage, and the contact resistance is so small that the current is higheven at the same voltage. That is, this embodiment can have the smallcontact resistance and good Ohmic contact. In this case, a two-layeredstructure including the first layer 50 a of titanium (Ti) and the secondlayer 50 b of ruthenium oxide (RuO₂) is used as the source/drainelectrode 50. The interface layer 50 c is formed at a boundary betweenthe titanium (Ti) and the oxide semiconductor layer (SnO).

In the structure of this embodiment, the interface layer 50 c isintroduced into a contacting part to the P-type oxide semiconductorlayer 30, which can reduce the Schottoky effect by reduction of theoxides or the like. Thus, this embodiment can form the Ohmic contactwith the P-type oxide semiconductor layer. Such a conductive oxide canalso be applied to the wide-gap semiconductor (for example, GaN, SiC)having a band gap of 2 eV or more.

Seventh Embodiment

The structure of a semiconductor device in a seventh embodiment of theinvention will be described below. The semiconductor device of thisembodiment differs from the semiconductor device of the sixth embodimentin the use of the same material to form the source/drain electrodes forthe N-type oxide semiconductor and the P-type oxide semiconductor. Now,the differences will be mainly described.

In the CMOS structure of this embodiment, byway of example, InGaZnO isused as the N-type oxide semiconductor layer 30 serving as an N-typefield-effect transistor (NFET) channel, and SnO is used as the P-typeoxide semiconductor layer 30 serving as a P-type field-effect transistor(PFET) channel. The source/drain electrode 50 for either the InGaZnO ofthe N-type oxide semiconductor layer 30 or the SnO of the P-type oxidesemiconductor layer 30 uses titanium (Ti)/aluminum (Al) or aluminumalloy (AlCu) in manufacturing. In this case, the first layer 50 a ismade of titanium (Ti), and the second layer 50 b is made of aluminum(Al) or an aluminum alloy (AlCu).

The semiconductor device of this embodiment can be manufactured by thesame method as in the first to fourth embodiments. The manufacturingmethod of the semiconductor device in this embodiment does not need theindividual manufacturing processes in formation of the contact unlikethe fifth and sixth embodiments. The source/drain electrode 50 for eachof the N-type oxide semiconductor layer 30 and the P-type oxidesemiconductor layer 30 uses titanium (Ti)/aluminum (Al) inmanufacturing.

In this case, the inventors have studied and got the following facts.After manufacturing the semiconductor device, Ti of Ti/Al keeps metallicat an interface between InGaZnO of the N-type oxide semiconductor layer30 and Ti of the first layer 50 a. That is, the interface layer 50 c canbe formed of Ti, which is the same as that of the first layer 50 a. Thisembodiment can achieve the low resistance contact to InGaZnO. Incontrast, the interface between SnO of the P-type oxide semiconductorlayer 30 and Ti of the first layer 50 a will be as follows. FIG. 18shows a schematic cross-sectional view of the composition of aninterface between the P-type oxide semiconductor layer and thesource/drain electrode of the semiconductor device in this embodiment.This figure shows the interface evaluated by an XPS (x-ray photoelectronspectroscopy). As shown in the figure, at the interface between theP-type oxide semiconductor layer 30 (SnO) and the source/drain electrode50 (Ti/Al), Ti positioned on the SnO side of Ti/Al partially drawsoxygen from SnO to reduce the resistance of the SnO, and is oxidizeditself to become TiOx. The interface layer 50 c can be a TiOx/SnOxtransition (x<1) unlike the first layer 50 a. In the TiOx/SnOxtransition layer, the ratio of TiOx to SnOx and the oxidation numbergradually changes, which leads to the reduction of SnO and thecoexistence of TiOx and SnOx. On the side of the TiOx/SnOx closer to Ti,TiOx is dominant. The compound TiOx is effective to reduce the contactresistance to the P-type oxide semiconductor like the sixth embodiment.The above process can reduce the contact resistance to SnO.

The above contact materials are evaluated as follows. FIG. 19 shows across-sectional view of an element structure for measuring theproperties of the semiconductor device in this embodiment. In order toevaluate the properties of the contact materials, the CV characteristicsare measured based on the element structure shown in the figure. Theelement structure includes a SnO film (of 100 nm in thickness) formed asthe P-type oxide semiconductor over a Si substrate with a SiO₂ filmattached thereto, and a SiO₂ film (of 50 nm in thickness) formed as agate insulating film over the SnO film. An Au film is provided as onegate electrode over the gate insulating film, and a film (of metal) ofthe contact material of this embodiment is provided as the otherelectrode over the SnO film.

FIG. 20 shows a graph of the properties (evaluation results) of thesemiconductor device in this embodiment. In FIG. 19, a longitudinal axisindicates a capacity, and a horizontal axis indicates a voltage. Asshown in the figure, the use of the Ti(first layer 50 a)/AlCu(secondlayer 50 b) as the film of the contact material (Metal) can increase thecapacity C as compared to the used of an Au(gold) film. This is becausea component of the contacting part contributing to the parasiticresistance is reduced to restore the capacity C. The use of the In(ITO)which is an oxide conductor described in the fifth embodiment can alsoincrease the capacity C for the same reason.

As mentioned above, in this embodiment, the same contact material isused for the N-type oxide semiconductor and the P-type oxidesemiconductor in manufacturing, but is found to become the differentkinds of contact materials in checking the properties aftermanufacturing of the semiconductor device. That is, in this embodiment,the contact for the P-type oxide semiconductor is formed of the samematerial (for example, Ti) as that of the contact for the N-type oxidesemiconductor. However, as a result, the material of the contact for theP-type oxide semiconductor becomes different from that of the N-typeoxide (for example, Ti versus TiOx). In other words, the material (forexample, Ti) is used which exhibits different behaviors (for example, ofTia and TiOx) with respect to the different oxide semiconductors (forexample, of InGaZnO and SnO). Without the individual manufacturingprocesses, the low resistance contacts (including the Ohmic contact tothe P-type oxide semiconductor) can be formed for both the oxidesemiconductors.

The fifth to seventh embodiments of the invention can be described asfollows, but the invention is not limited thereto.

(Additional Statement 1)

The present invention provides a semiconductor device, including: afirst transistor (200) of a first conductive type serving as onetransistor forming a CMOS; and

a second transistor (300) of a second conductive type other than thefirst conductive type, serving as another transistor forming the CMOS,

wherein the first transistor (200) and the second transistor (300)differ from each other in material or property of the source/drainelectrodes (289 and 389).

(Additional Statement 2)

In the semiconductor device described in the additional statement 1,each of the first transistor (200) and the second transistor includes:

a gate electrode (210/310);

a gate insulating film (171) formed over the gate electrode (210, 310);

an oxide semiconductor layer (230/330) formed over the gate insulatingfilm (171); and

a source/drain electrode (289/389) formed over the oxide semiconductorlayer (230/330),

wherein the source/drain electrode (289/389) for a P-type transistorwhich is one of the first transistor (200) and the second transistor(300) has a contacting part with the oxide semiconductor (230/330) as aP-type oxide semiconductor layer of the P-type transistor, thecontacting part containing a conductive oxide or another P-type oxidesemiconductor.

(Additional Statement 3)

In the semiconductor device described in the additional statement 2, thecontacting part contains at least one material selected from the groupcomprised of ruthenium oxide, tin-doped indium oxide, and titaniumoxide.

(Additional Statement 4)

In the semiconductor device described in the additional statement 1,each of the first transistor (200) and the second transistor includes:

a gate electrode (210/310);

a gate insulating film (171) formed over the gate electrode (210, 310);

an oxide semiconductor layer (230/330) formed over the gate insulatingfilm (171); and

a source/drain electrode (289/389) of the oxide semiconductor layer(230/330),

wherein the source/drain electrode (289/389) for a P-type transistorwhich is one of the first transistor (200) and the second transistor(300) has a contacting part with the oxide semiconductor layer (230/330)as a P-type oxide semiconductor layer of the P-type transistor, thecontacting part containing metal for forming an interface layer (50 c)formed by partially modifying at least one of the oxide semiconductorlayer and the source/drain electrode (289/389).

(Additional Statement 5)

In the semiconductor device described in the additional statement 4, thecontacting part contains titanium oxide.

(Additional Statement 6)

In the semiconductor device described in the additional statement 5,wherein the source/drain electrode (289/389) for an N-type transistorwhich is the other of the first transistor (200) and the secondtransistor (300) has a contacting part with the oxide semiconductorlayer (230/330) as an N-type oxide semiconductor layer of the N-typetransistor, the contacting part containing titanium.

The present invention made by the inventors has been specificallydescribed based on the preferred embodiments, but it is apparent thatthe invention is not limited thereto, and that various modifications andchanges can be made without departing from the scope of the invention.The respective preferred embodiments and techniques of the modifiedexamples of the embodiments can also be applied to other embodiments aslong as they are not technically contradictory.

1-18. (canceled)
 19. A method for manufacturing a semiconductor device,comprising the steps of: (a) forming a first wiring over a semiconductordevice; (b) forming a first interlayer insulating layer over the firstwiring; (c) forming a first gate electrode and a second gate electrodeso as to be embedded in the first interlayer insulating layer; (d)forming a first semiconductor layer via a first gate insulating filmover the first gate electrode; (e) forming a first insulating film overthe first insulating layer so as to cover the first semiconductor layer;(f) forming a sidewall film to cover a side of the first semiconductorlayer by etching the first insulating film; (g) after step (f), forminga second semiconductor layer via a second gate insulating film over thesecond gate electrode.
 20. The manufacturing method of the semiconductordevice according to claim 19, wherein the first and second gateinsulating films are formed at the same time and are formed betweensteps (c) and (d).
 21. The manufacturing method of the semiconductordevice according to claim 20, wherein after step (f), the second gateinsulating film is thinner than the first gate insulating film.
 22. Themanufacturing method of the semiconductor device according to claim 19,wherein a first transistor comprises the first gate electrode, the firstgate insulating film and the first semiconductor layer, wherein a secondtransistor comprises the second gate electrode, the second gateinsulating film and the second semiconductor layer, and wherein thefirst transistor and the second transistor are transistors of oppositeconductive types to form a complementary metal-oxide semiconductor. 23.The manufacturing method of the semiconductor device according to claim22, wherein the first transistor is p-type, wherein the secondtransistor is n-type.
 24. The manufacturing method of the semiconductordevice according to claim 19, wherein the first semiconductor layer andthe second semiconductor layer include an InGaZnO layer, an InZnO layer,a ZnO layer, a ZnAlO layer, a ZnCuO layer, a NiO layer, a SnO layer, aSnO₂ layer, a CuO layer, a Cu₂O layer, a Ta₂O₅ layer or a TiO₂ layer.25. The manufacturing method of the semiconductor device according toclaim 19, wherein the second gate insulating film is thinner than thefirst gate insulating film.
 26. The manufacturing method of thesemiconductor device according to claim 24, further comprising steps of:(h) forming a second interlayer insulating layer over the first andsecond semiconductor layers, and (i) by etching the second interlayerinsulating layer, forming a first contact hole on the firstsemiconductor layer and forming a second contact hole on the secondsemiconductor layer.